Modern memory integrated circuits, particularly read/write circuits such as static random access memories (SRAMS) and dynamic random access memories (DRAMs), are becoming quite large in physical size and in the density of memory locations therein. For example, SRAMs with 2.times..sup.20 addressable locations and DRAMs with 2.sup.22 addressable locations are now readily available. Even with submicron feature sizes, the physical size of the integrated circuit chip containing such memories can be as large as on the order of 180 kmil.sup.2. In addition, many complex microprocessors now include significant amounts of on-chip memory, such as 64 kbytes or more of read-only memory and 64 kbytes or more of random access memory. The physical chip size of some of these modern microprocessors may be as large as on the order of 250 kmil.sup.2.
It is well known that as the minimum feature size in integrated circuit chips becomes smaller, the size of defect that can cause a failure (i.e., the size of a "killing" defect) also shrinks. As a result, especially with large chip sizes, it is more difficult to achieve adequate manufacturing yield as the size of a killing defect reduces. In order to reduce the vulnerability of a relatively large integrated circuit chip to a single small defect, modern integrated circuits utilize spare rows and columns that can be used to replace defective rows and columns, respectively, in the memory portion of the circuit. Substitution of one of the spare rows or columns is conventionally accomplished by the opening of fuses (or closing of antifuses, as the case may be) in decoder circuitry, so that access is made to the spare row or column upon receipt of the address for the defective row or column in the primary memory array. Conventional fuses include polysilicon fuses which can be opened by a laser beam, and also avalanche-type fuses and antifuses.
Examples of memory devices incorporating conventional redundancy schemes are described in Hardee, et al., "A Fault-Tolerant 30 ns/375 mW 16K.times.1 NMOS Static RAM", J. solid State Circuits, Vol. SC-16, No. 5 (IEEE, 1981), pp. 435-43, and in Childs, et al., "An 18 ns 4K.times.4 CMOS SRAM", J. Solid State Circuits, Vol. SC-19, No. 5 (IEEE, 1984), pp. 545-51. An example of a conventional redundancy decoder is described in U.S. Pat. No. 4,573,146, issued Feb. 25, 1986, assigned to SGS-Thomson Microelectronics, Inc., and incorporated herein by this reference.
Of course, these spare rows and columns require additional chip area for their implementation. Indeed, it has been observed that provision of too many spare rows and columns can add, rather than save, manufacturing cost, if the cost of the chip area required for the spare elements and their decoders outweighs the yield improvement achieved by use of the spare elements. Accordingly, the number of spare rows and columns must be selected considering expected defect density. Besides selection of the number of spare elements, effective redundancy schemes must consider the type of defects likely to be encountered, so that the spare elements match the expected failure type and manifestation.
As can be expected, the organization of the memory array is also a large factor in selecting the number of spare elements to be implemented. For purposes of power reduction, many high density memories are now organized into sub-arrays, or blocks, so that only a portion of the memory need be energized in a given access, resulting in significant power reduction. Power dissipation is of especially high concern for integrated circuit memories intended for use in applications, such as portable computers, which are powered from batteries. Copending application Ser. No. 588,600, filed Sept. 26, 1990, assigned to SGS-Thomson Microelectronics, Inc., and incorporated herein by this reference, describes a memory having such a partitioned array.
While such partitioned memories provide significant, and in some cases essential, power reduction, the organization of the primary memory into sub-arrays makes more costly the assignment of spare elements, particularly redundant columns. As the number of sub-arrays or blocks increases, for example up to sixteen or thirty-two blocks, the chip area cost of providing spare columns for each becomes quite high. As a result, fewer columns may be provided per block, which of course reduces the numbers of defects which can be "repaired" by use of the spare columns.
Further exacerbating the difficulty of efficiently providing redundant columns is the common use of multiple input/output terminals in modern RAMS. many RAms provide eight or sixteen simultaneous outputs; for example, the memory of the above-noted copending application Ser. No. 588,600 accesses eight bits (all in the same block) with each memory address. Assignment of one column per input/output per block can greatly increase the chip area required, while only assigning one column per input/output per block can limit the repairability yield (i.e., the fraction of memories built which can be saved by use of the spare columns).
It is therefore an object of the present invention to provide an integrated circuit having a memory column redundancy architecture which can map a redundant column into multiple block addresses.
It is another object of the present invention to provide such a circuit in which a redundant column can be mapped to one of several input/output terminals.
It is another object of the present invention to provide such a circuit in which the programming of the address assignment of the redundant columns is relatively simple.
It is another object of the present invention to provide such a circuit in which the performance loss in accessing a redundant column is minimized or eliminated.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.